In modern computers, it is common to pre-fetch instructions. Then, when it is time to execute a next instruction, the instruction will readily be available. If instructions are fetched ahead of time, delays can be avoided. Normally, instructions are executed in a sequential order with respect to their addresses as maintained by a program counter (PC). Therefore, normal sequential pre-fetching is simple to perform.
However, some instructions are fetched from non-sequential addresses. For example, branch and jump instructions change the PC to a non-sequential address. In order to allow the pre-fetching of instructions from non-sequential addresses, the instructions may include "hint" fields. For example, on the ALPHA processor made by Digital Equipment Corporation, Maynard, Mass., a 16 bit hint field is provided with branch-to-subroutine, and jump-to-subroutine instructions.
The hint field, in part, specifies the low order bits of a likely target address. The low bits are enough to specify an address of an instruction-cache block. The hint field allows branch prediction logic of a processor to start an early instruction fetch from the likely target address. A correct prediction can save five to six cycles for certain ALPHA processors.
In most prior art applications, hint fields of instructions are statically determined when source code modules are processed to produce machine executable code. Static hint field predication is limited to determining hint fields for instructions where the target address is absolutely known. For example, the target address is the first instruction of a procedure of a shared library whose load address can be predetermined.
However, in object oriented programming using, for example, the C++ language, it is common to indirectly call a procedure (method) via a variable which is dynamically resolved at run-time. Obviously, in this situation, the likely target address cannot be predicted prior to run-time, and, the hint field cannot be set statically, e.g., the hint field is null. Consequently, instructions which are indirectly fetched in a non-sequential manner can cause delays. A solution is desired.